Event Information


Variation-aware high-level DSP circuit design optimisation framework for FPGAs
ISR Amphitheater

Seminar by Rui Duarte

Frequently, applications such as image and video processing rely on implementations of the Linear Projection algorithm with high throughput and low latency requirements. This work presents a framework to optimise Linear Projection designs that excel typical design implementations via a pre-characterisation of over-clocked arithmetic units. It is well known that the delay models used by synthesis tools are generic and tuned for the worst performance possible of a given fabrication process. Hence, they impose a heavy penalty in the possible maximum performance offered by the fabrication process. The proposed optimisation framework focuses on the optimisation of the generic multipliers, as they are the arithmetic operators with the most critical paths in the data path of a linear projection design, by performing a performance characterisation step on the target device. Experiments demonstrate that the proposed framework is able to generate Linear Projection designs that achieve higher throughput (up to 1.85 times) while producing less errors than typical implementation methodologies.

Rui Duarte’s short bio:
Rui Duarte is concluding a PhD in Electrical and Electronic Engineering from Imperial College London, with the thesis “Variation-Aware High-Level DSP Circuit Design Optimisation Framework for FPGAs”. He holds a MSc in Electrical and Computer Engineering from Instituto Superior Técnico. His research interests include SoC FPGA Design for Digital Image and Video Processing, Reconfigurable and Resilient architectures, and Computer Networking. He has joined AP4ISR recently to work in the BAMBI project as a PostDoc Research Associate.