BAYpP - Bayesian Processor on FPGA
We want to develop the building blocks and the architecture for Bayesian probabilistic processors, and apply them in robotic systems. This will bridge the results from neuromorphic computing with robotics applications, in a bottom up approach addressing subsets of a full brain simulation. We envision a new paradigm for hardware/software, where a Bayesian program is spooled onto a reconfigurable substrate, with part of the program mapped to the topology of the interconnected inherently parallel hardware, and not in software. These devices will draw much less power than current solutions, and eventually store probability variables in an analogue way. We will follow a bottom up approach, form the low level concept of Bayesian gates, moving up on how these can be assembled into modular architectures to instantiate Bayesian complex computations. Our implementation will rely strongly on reconfigurable logic to emulate probabilistic gates, so that a working model of the architecture can be implemented, and later ported to emerging devices. As the limits of current technologies are reached, new technologies emerge. A very promising emerging technology is the memristor, that used as a switching device will allow a big step in FPGAs (reconfigurable logic devices) by providing a nanowire programmable interconnect to be placed above the CMOS layer, so that logic densities of reconfigurable devices can approach hardwired application specific integrated circuits (ASIC).
Supervisor: Prof. Jorge Lobo