Probabilistic Computing on FPGA with NIOS II soft-processor
The aggressive scale down in process technology, to increase its performance and reduce its power, has led to nano-devices with increased variation and limited resilience, exhibiting a stochastic behavior, inspired by biochemical cell signaling. We plan to take advantage of the uncertainty exhibited by new devices, and emulate its behavior on an FPGA.
Moreover, we plan to create a stochastic accelerator, using Bayesian gates, and integrate it in an embedded system as means to improve the efficiency of a DSP application (performance / power). Bayesian gates operate on probability distributions on binary variables as the building blocks of our probabilistic algebra. These Bayesian gates can be seen as a generimalization of logical operators in Boolean algebra.
In this research project you will investigate the implementation of probabilistic computation accelerator as part of an embedded system using Altera's soft-processor NIOS II.
The following tasks are planned for this topic: T1 requirement assessment, decision on the approach and training in implementing and debugging embedded systems using Qsys/Modelsim; T2 design the stochastic accelerator; T3 integration of the stochastic accelerator in the embedded system; T4 experimental validation of the solution; T5 writing the final dissertation. The end result is a dissertation and an implementation of the stochastic accelerator for NIOS II.
Supervisor::Prof. Jorge Lobo (DEEC-FCTUC)
Co-supervisor::Dr. Rui Duarte (ISR Coimbra)
This work is within the scope of the BAMBI European FET Project (FET Project - FP7-ICT-2013-C). The project takes a bottom-up approaches to building machines dedicated to Bayesian inference. Within the BAMBI consortium, ISRUC is working on the emulation hardware implementation and on the computational architecture to be developed, namely in the composition of basic building blocks for probabilistic computation. http://mrl.isr.uc.pt/projects/bambi/
- P. Bessière, J-M. Ahuactzin, K. Mekhnacha, and E. Mazer, Bayesian Programming, Chapman and Hall/CRC, 213.
- A. Alaghi and J. P. Hayes, “Survey on Stochastic Computing,” ACM, January 2013.
- Altera's NIOS II - http://www.altera.com/devices/processor/nios2/ni2-index.html
The work will be carried out at the Institute of Systems and Robotics, ISR, in a lab fully equipped for FPGA prototyping and artificial perception. For more details, please contact firstname.lastname@example.org and visit http://ap.isr.uc.pt.